Data Types Register variables store the last value that was procedurallyassigned to them wire variables represent physical connections between structural entities such as gates – does not store anything, only a label on a wire Verilog Constructs and Modeling Styles You can write module at four levels of abstractions Behavioural (Algorithmic like C) Dataflow (How […]
Capacitance generated between Channel(Source, Drain, Bulk) and Gate. In cutoff there isn’t any channel present and therefore there is Cgc between gate and body. In linear region inversion layer if formed. The Layer is between source and drain. Thus gate to body capacitance is 0 and total Cgc is distributed evenly between source and drain. […]
Programmable Logical Device : A programmable logic device (PLD) is an electronic component used to build reconfigurabledigital circuits. Unlike integrated circuits (IC) which consist of logic gates and have a fixed function, a PLD has an undefined function at the time of manufacture.[1] Before the PLD can be used in a circuit it must be programmed (reconfigured) by using a specialized program CPLDs can replace thousands, […]
We have seen CMOS before and we will keep on seeing it as long as we are planning to remotely associate ourselves with VLSI. To recall, why we bother with CMOS at all–Let’s look at the following points. Some History Lesson Kids : Silicon is a Group IV element, so it forms covalent bonds with […]
As the fate might have this, I am here again, a day before my viva, doing VLSI. Welcome to VLSI by an amateur who’s just trying to pass college exams. Warning: I know nothing, everything in this blog may or may not be write–or even make any sense. Taming the beast-Microwind Microwind is a tool […]
Hamming code is linear error block code used to encode input. Hamming codes can detect up to two-bit errors or correct one-bit errors without detection of uncorrected errors. Parity Bits in Hamming Code : TestBench: Expected Output 0000 0000000 0001 1101001 0010 0101010 0011 1000011 0100 1001100 0101 0100101 0110 1100110 0111 0001111 1000 1110000 […]
There are a lot of delays in verilog, and trust me when I say I am done with them! There is your normal delay But there you can have a delay with identifier You can also now have an expression Then there is minimum, typical and maximum delay but they are further divided into rise […]
Welcome back, I am here, writing another blog as I struggle to understand the syllabus for my t2 exam. To anyone who’s reading this for the first time, let me give you some context. Whenever I am conflicted about what I am studying I write a blog. This is also helpful whenever I have to […]
Expressions They combine operators and operands. This is pretty similar to a normal expression in any language. Let’s talk about some interesting one Case Equality/inequality : Equates using x and z Reduction : Reduces it down to one bit by doing interbit operation Concatenation : Literally concatenates the binary numbers Replication : Concatenates and then […]
Do I like studying like this? No. Do I have to if I want to clear this course? Yes. These are my notes of Third and Fourth chapter from Verilog HDL: A Guide to Digital Design and Synthesis, Second Edition. By Samir Palnitkar. Let’s go through the steps We know Full Adder is two Half Adder […]