## Verilog : Hamming Code On FPGA

Hamming code is linear error block code used to encode input. Hamming codes can detect up to two-bit errors or correct one-bit errors without detection of uncorrected errors. Parity Bits in Hamming Code :  TestBench:  Expected Output 0000 0000000 0001 1101001 0010 0101010 0011 1000011 0100 1001100 0101 0100101 0110 1100110 0111 0001111 1000 1110000 […]

Disclaimer: If I didn’t graduate college because I failed by Computer Networks course, this, right now, is the time I will look back and realise –“This is where it all went downhill” Regardless of that, writing blogs helps me retain a lot of stuff. Even though my idea of studying for this the literal last […]

## Verilog: Delay Delay Everywhere

There are a lot of delays in verilog, and trust me when I say I am done with them! There is your normal delay But there you can have a delay with identifier You can also now have an expression Then there is minimum, typical and maximum delay but they are further divided into rise […]

## Verilog: Gate Level Multiplexers

Welcome back, I am here, writing another blog as I struggle to understand the syllabus for my t2 exam. To anyone who’s reading this for the first time, let me give you some context. Whenever I am conflicted about what I am studying I write a blog. This is also helpful whenever I have to […]

## Verilog: Dataflow Modeling

Expressions They combine operators and operands. This is pretty similar to a normal expression in any language. Let’s talk about some interesting one Case Equality/inequality : Equates using x and z Reduction : Reduces it down to one bit by doing interbit operation Concatenation : Literally concatenates the binary numbers Replication : Concatenates and then […]

## Verilog: Adders, Ports, Gate Level Modeling, Multiplexer

Do I like studying like this? No. Do I have to if I want to clear this course? Yes. These are my notes of Third and Fourth chapter from  Verilog HDL: A Guide to Digital Design and Synthesis, Second Edition. By Samir Palnitkar. Let’s go through the steps We know Full Adder is two Half Adder […]

## Verilog : Hierarchical Modeling Concepts

Turns out, I have a course in VLSI and today happens to be the first time I am opening up my textbook. To add to this spicy spicy story, it’s also the day (night) before my exam. Before you start freaking out and giving up on me, let me tell you one thing. IT IS […]