Vaguely Related to ETC

Programmable Logical Device

CPLD Architecture

Take Aways :

  • Complex Programmable Logical Device.
  • Contains input/out, programmable interconnect and PLDs
  • PLDS will have Programmable AND array, Product Term and 18 Macrocells

Reference

Programmable Logical Device : A programmable logic device (PLD) is an electronic component used to build reconfigurabledigital circuits. Unlike integrated circuits (IC) which consist of logic gates and have a fixed function, a PLD has an undefined function at the time of manufacture.[1] Before the PLD can be used in a circuit it must be programmed (reconfigured) by using a specialized program

CPLDs can replace thousands, or even hundreds of thousands, of logic gates.
Complex Programmable Logic Device (CPLD) is a combination of a fully programmable AND/OR array and a bank of macrocells. 

Some of the CPLD features are in common with PALs:

  • Non-volatile configuration memory. Unlike many FPGAs, an external configuration ROM isn’t required, and the CPLD can function immediately on system start-up.
  • For many legacy CPLD devices, routing constrains most logic blocks to have input and output signals connected to external pins, reducing opportunities for internal state storage and deeply layered logic. This is usually not a factor for larger CPLDs and newer CPLD product families.

Why PLDS?

  • First, there is reasonable integration ability, allowing implementation of a significant amount of functionality into one physi- cal chip.
  • Programmable logic devices remove the need for multiple off-the-shelf devices along with the inconvenience and unreliability associated with external wires.
  • Second, there is the increased ability to change designs. Many of the pro- grammable devices allow easy reprogramming.

In general, a CPLD is an IC that consists of a number of PAL-like logic blocks together with a programmable inter- connect matrix.

CPLDs typically contain 500 to 10,000 logic gates

It is expensive to build these switches; however, use of such a switch results in predictable timing.

Each macrocell contains a flip-flop and an OR gate, which has its inputs connected to an AND gate array.

Function Block

It had three parts.

  • Programmable AND array
  • Product term allocators
  • 10 Macrocell with 1 Global Set/Reset and 3 global clock
  • Programmable AND array gets 36 fast connect II switch matrix
  • Output
    • 18 output
    • 18 PTOE
    • 8 Fast Connect II switch matrix

MacroCell

FPGA Architecture

Take Aways :

  • Field Programmable Gate Array
  • Made up of programmable IO block, Programmable logic block and programmable interconnect.
  • Configurable Block Contains four slice with two LC
  • LC
    • Look Up Table
    • MUX
    • Data Inputs and Outputs
    • Clock
    • Clock enable
    • set/reset
    • Signal
  • Can be programmed using
    • MUX based implementation
    • LUT based implementation

Configurable Logic Block

  • Contains four slice with two LC

The Slice

  • LC
    • LUT – Look Up Table
    • MUX
    • Data Inputs and Outputs
    • Clock
    • Clock enable
    • set/reset
    • Signal

FPGA can use any of the following programming techniques

  • SRAM
  • Antifuse
  • Flash
  • Hybrid-FLASH-SRAM

Logic Realisation

  • MUX based
  • LUT based

MUX Based

Based on Shannon’s decomposition theorem which states that let f(x) be a switching function of n variables then f(a) can be factored as

f(a) = ai.f1 + ai’.f2

??

LUT Based

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