## CMOS

• Complementary Metal Oxide Semiconductor
• Low Power Deception
• Consists of pMOS (Active Low) and nMOS (Active High). MOS is basically an ON and OFF switch
• Current can be adjusted by adjusting the width of the gate (Directly Proportional)

We have seen CMOS before and we will keep on seeing it as long as we are planning to remotely associate ourselves with VLSI. To recall, why we bother with CMOS at all–Let’s look at the following points.

## CMOS – Complementary metal-oxide semiconductor

• CMOS has much lower power dissipation compared to its other BIPOLAR counterparts. * Insert inappropriate mental health jokes *
• Complementary MOS circuit has almost no static power dissipation.
• Complementary Metal Oxide Semiconductor transistor consists of P-channel MOS (PMOS) and N-channel MOS (NMOS). Please refer the link to know more about the fabrication process of CMOS transistor.
• Gate – Current is controls whether the device will be on or off.
• Drain and Source are identical, generally, the labelling convention says that terminal with higher potential is labelled as drain.
• Current from Drain to source is proportional to width of gate divided by length
• $I_{DS} = W/L$

Some History Lesson Kids : Silicon is a Group IV element, so it forms covalent bonds with four adjacent atoms. The lattice is shown in the plane for ease of drawing, but it actually forms a cubic crystal. As all of its valence electrons are involved in chemical bonds, pure silicon is a poor conductor.

When the voltage on the p-type semiconductor, called the anode, is raised above the n- type cathode, the diode is forward biased and current flows.

Gate : Insulating layer of silicon (SiO2 or —GLASS)
Substrate : Silicon Wafter

Gates of early transistors were built from metal, so the stack was called metal- oxide-semiconductor, or MOS. Since the 1970s, the gate has been formed from polycrystalline silicon (polysilicon), but the name stuck.

An nMOS tran- sistor is built with a p-type body and has regions of n-type semiconductor adjacent to the gate called the source and drain. A pMOS transistor is just the opposite, consisting of p-type source and drain regions with an n-type body.

#### How to remember this? Whatever is the suffix behind the MOS (p/n) has source and drain of that material and body of the opposite.

In a CMOS technology with both flavors of transistors, the substrate is either n-type or p-type. The other flavor of transistor must be built in a special well in which dopant atoms have been added to form the body of the opposite type.

#### Who tf are you ft. Gate:

Description : Gate is control input.
Responsibility : Controls flow between source and drain.

Consider an nMOS transistor. The body is generally grounded so the p–n junc- tions of the source and drain to body are reverse-biased. If the gate is also grounded, no current flows through the reverse-biased junctions. Hence, we say the transistor is OFF. If the gate voltage is raised, it creates an electric field that starts to attract free electrons to the underside of the Si–SiO2 interface. If the voltage is raised enough, the electrons out- number the holes and a thin region under the gate called the channel is inverted to act as an n-type semiconductor. Hence, a conducting path of electron carriers is formed from source to drain and current can flow. We say the transistor is ON.

In popular logic families of the 1970s and 1980s, VDD was set to 5 volts. Smaller, more recent transistors are unable to withstand such high voltages and have used supplies of 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, 1.0 V, and so forth. The low voltage is called GROUND (GND) or VSS and represents a logic 0. It is normally 0 volts.

#### Who tf are you ft. Drain:

Description : The drain is connected to the load,
Responsibility : Drive load from Vdd to source.

#### Who tf are you ft. Source:

Description : The source is connected to ground (or the positive voltage, in a p-channel MOSFET
Responsibility : Drive current to ground or VDD

## MOSFET Parasitics

Because a transistor gate is a good insulator, it can be modeled as a capacitor, C. When the transistor is ON, some current I flows between source and drain. Both the current and capacitance are proportional to the transistor width.

$I = C \frac{dV}{dt}$

If an average current I is applied, the time t to switch between 0 and VDD is

$t = \frac{C}{I}V_{DD}$

#### Gate Capacitance

Channel Charge and MOS charge.

Refer to notes on parasitic capacitance

## Technology Scaling

Take Aways :

• Reduction of Dimensions is called scaling.
• Technology Scaling involves scaling dimensions of the MOSFET without a lot change in it’s characteristics
• The value of $\alpha$ is typically ~ 0.7 from one CMOS technology generation to the next.

Interesting Facts

• The shrinking of transistors to dimensions below 100 nm enables hundreds of millions transistors to be placed on a single chip.
• Moore’s law “Cramming morecomponents onto integrated circuits” in 1965 In this publication provided that the number of active transistor per chip doubled roughly every year.

Reference

Others

• What is technology scaling? Explain three ways of scaling the devices?
• Explain different Design Rule in terms of $\lambda$ parameters
• What do you mean by scaling in CMOS VLSI circuits?

We introduce dimensionless factor $\alpha$ to preserve basic operational characteristics.

Reduction of lateral dimensions of the MOSFET and interconnects size is known as scaling of the geometric dimensions of MOSFET

• Improved current driving capability improves device characteristics
• Due to small geometries the capacitance is reduced.
• Improved interconnect technology reduces RC delay
• Multiple threshold devices due to scaling adjusts the active and stand by power tradeoffs
• The integration density improves due to single chip devices.
• Enhanced performance in terms of speed and power consumption
• Cost of chop is decreases by twice

• Power Consumption per unit area increases as devices are scaled down. That means that scaled devices run increasingly hot.
• Mistakes of having scale proportionally to zero dimension or to zero threshold voltages.
• Since scaling reduces the carrier mobility, grain of the device reduces.
• Dude to reduction in conductor size the current handelling capacity of the device reduce. To solve this addition metal layers are necessary for more densely packed structure.

### Types of scaling

• Constant field Scaling.

Substrate Doping scaled by $\alpha$

Channel length, width, depletion layer thickness, gate delay, load capacitance, supply voltage, Gate Oxide Thickness, Current, Junction Depth are all scaled by $\frac{1}{\alpha}$

Transconductance remains the same

Static and dynamic powers are scaled by $\frac{1}{{\alpha}^2}$

• Constant Voltage Scaling

Substrate Doping, transconductance Static and dynamic powers, Current scaled by $\alpha$

Channel length, width, depletion layer thickness, gate delay, load capacitance, supply voltage, Gate Oxide Thickness, Junction Depth are all scaled by $\frac{1}{\alpha}$

Supply voltage remains the same

Gate Delay scaled by $\frac{1}{{\alpha}^2}$

current density is scaled by ${\alpha}^3$

• Lateral Scaling

Substrate Doping, transconductance Static and dynamic powers, Current scaled by $\alpha$

Channel length, width, gate delay, load capacitance are all scaled by $\frac{1}{\alpha}$

channel width remains the same

Gate Delay, junction depth, substrate doping, depletion layer thickness, supply voltage, gate oxide thickness scaled by $\frac{1}{{\alpha}^2}$

current density is scaled by ${\alpha}^2$

## Channel Length Modulation

Take Aways :

• Increase in Vds results in increase in depletion region at drain junction and effectively increasing channel length
• $\frac{\delta L}{L} = \lambda V_{DS}$

Interesting Facts

• In textbooks, channel length modulation in active mode usually is described using the Shichman–Hodges model, accurate only for old technology:

Reference

Effective length of conductive channel L’ is modulated by $V_{DS}$

Increase in $V_{DS}$ -> Depletion region at drain junction increases->Reduces effective channel length.

$L' = L- \delta L$

or

$\frac{\delta L}{L} = \lambda V_{DS}$

## Body Effect

Take Aways :

• When increase in Vdd results in the voltage of bulk dropping then the depletion charge increases. This is called body effect.
• This results in change in threshold voltage

Assumption : Bulk and Source tied to ground

Like all infinities aren’t the same, all grounds aren’t–What happens when bulk voltage of nMOS drops below source voltage.

Theshold voltage is function of total charge in the depletion region thus as gate voltage increases body voltage drops and depletion charge increases.

This increases threshold and this effect is called body effect or back gate effect.

## Hot Electron Effect

Take Aways :

When nMOS transistor is operated in saturation region electrons are travelling with saturation velocity and cause parasitic effects at drain side of the channel.

This effects are called hot electron effects.

They can generate electron-hole pairs by impact ionisation

The generated majority carriers create a bulk current which can be used to measure the level of impact ionisation.

When nMOS transistor is operated in saturation region electrons are travelling with saturation velocity and cause parasitic effects at drain side of the channel.

This effects are called hot electron effects.

They can generate electron-hole pairs by impact ionisation

The generated majority carriers create a bulk current which can be used to measure the level of impact ionisation.

## Velocity Saturation

Take Aways :

• when electric field is increased beyond certain velocity called thermal velocity the carrier charger does not change with electric field.
• Saturation velocity for electrons and holes are $10^7$ cm/s
• $V_{DSSAT} = F (V_{GS}-V_{TH}).(V_{GS}-V_{TH})$
• $I_{DSSAT} = v_{sat} C_{ox}.W(V_{GS}-V_{TH}-V_{DSSAT}$

Velocity of Charge Carriers is linearly proportional to electric field and proportionality constant is called mobility of carrier.

When electric field is increased beyond certain velocity called thermal velocity the carrier charger does not change with electric field.

Saturation velocity for electrons and holes are $10^7$ cm/s

$V_{DSSAT} = F (V_{GS}-V_{TH}).(V_{GS}-V_{TH})$

$I_{DSSAT} = v_{sat} C_{ox}.W(V_{GS}-V_{TH}-V_{DSSAT}$

## Power Dissipations

Take Aways :

Energy is required to charge and discharge the load capacitance. This is called dynamic power because it is consumed when the circuit is actively switching. The dynamic power consumed when a capacitor is charged and discharged at a frequency f is

$P_{dynamic} = CV^{2}_{DD}f$

Even when the gate is not switching, it draws some static power. Because an OFF transistor is leaky, a small amount of current $latex I_{static}$ flows between power and ground, resulting in a static power dissipation of

$P_{static} = I_{static}V_{DD}$

Energy is required to charge and discharge the load capacitance. This is called dynamic power because it is consumed when the circuit is actively switching. The dynamic power consumed when a capacitor is charged and discharged at a frequency f is

$P_{dynamic} = CV^{2}_{DD}f$

Even when the gate is not switching, it draws some static power. Because an OFF transistor is leaky, a small amount of current $latex I_{static}$ flows between power and ground, resulting in a static power dissipation of

$P_{static} = I_{static}V_{DD}$

## CMOS Logic

CMOS Combinatorial Logic Design
Combinational circuits only depend on current inputs. It doesn’t have any memory

• You will need to create two networks, one pull up that draws he circuit to VDD and pull-down that draws it to GND
• Create these two separately
• Single Gate : pMOS when it’s active low and nMOS when it’s active high.
• Two gates :pMOS in series == A’ . B’ or (A+B)’
• pMOS in parallel == A’+B’ or (A.B)’
• nMOS in series == A.B or (A+B)
• nMOS in parallel == A+B or (A.B)
• Trick : Make the nMOS circuit, whenever nMOS is in series make pMOS in parallel and vice versa.
• Trick2:Use nMOS in circuits output node to ground(Logic 0) or pull down circuits
• Use pMOS in circuits output node to VDD(Logic 1) or pull up circuits

## CMOS Inverter

Inverter is simple idea. Whatever input you get, you give the opposite of it back.

Inverter Logic Table

Thus, we know that when input is 0, nMOS will be on and when input is 1 pMOS will be active.

#### Revision : DeMorgan’s Law

So when you’re trying to build any logical circuit using CMOS, convert the gate/equation into it’s simplified logical form. Then use the following rule

• You will need to create two networks, one pull up that draws he circuit to VDD and pull-down that draws it to GND
• Create these two separately
• Single Gate : pMOS when it’s active low and nMOS when it’s active high.
• Two gates :
• pMOS in series == A’ . B’ or (A+B)’
• pMOS in parallel == A’+B’ or (A.B)’
• nMOS in series == A.B or (A+B)
• nMOS in parallel == A+B or (A.B)
• Trick : Make the nMOS circuit, whenever nMOS is in series make pMOS in parallel and vice versa.
• Trick2:
• Use nMOS in circuits output node to ground(Logic 0) or pull down circuits
• Use pMOS in circuits output node to VDD(Logic 1) or pull up circuits

NOR CMOS

## CMOS-NOR

NOR CMOS

Trying out three input NOR gate

## Transmission Gates

The strength of a signal is measured by how closely it approximates an ideal voltage source. In general, the stronger a signal, the more current it can source or sink. The power sup- plies, or rails, (VDD and GND) are the source of the strongest 1s and 0s.

nMOS : Strong 0 but weak 1
pMOS : Strong 1 but weak 0

We term this a transmission gate or pass gate. In a circuit where only a 0 or a 1 has to be passed, the appropriate transistor (n or p) can be deleted, reverting to a single nMOS or pMOS device.

Note that both the control input and its complement are required by the transmission gate. This is called double rail logic. Some circuit symbols for the transmission gate. None are easier to draw than the simple schematic, so we will use the schematic version to represent a transmission gate in this book.

## Layout Design Rules.

• Layout design rules describe how small features can be and how closely they can be reliably packed in a particular manufacturing process

A conservative but easy-to-use set of design rules for layouts with two metal layers in an n-well process is as follows:

• Metal and diffusion have minimum width and spacing of 4 .
• Contacts are 2 × 2 and must be surrounded by 1 on the layers above and below.
• Polysilicon uses a width of 2 .
• Polysilicon overlaps diffusion by 2 where a transistor is desired and has a spacing of 1 away where no transistor is desired
• Polysilicon and contacts have a spacing of 3 from other polysilicon or contacts.
• N-well surrounds pMOS transistors by 6 and avoids nMOS transistors by 6

## MOS IV Characterstics

Voltage transfer characteristics is Vout vs Vin

Moores law–24 months 2x smaller.

Gate and Substrate form a capacitor. MOSFET is four terminal Field Effect transistor. Highest voltage potential Drain. Current will flow from drain to source.

Vth is threshold – Switch from open to closed. Vth ~ half a voltage. MOSFET is controlled by $V_{gs} = V_{g} - V_{s}$

If $V_{gs} Open switch depletion region is small.

$V_{gs} >V_{th}$ and $V_{ds} < V_{gs}-V_{th}$

$I_{ds} = \frac{V_{ds}}{R}$

BUTTTTT

if $V_{gs} >V_{th}$ and $V_{ds} > V_{gs}-V_{th}$ PINCH OFF

When inversion happens fermi potential is reached which is

Holy shit, I hope none of this comes for exam. Really. I really hope that.

## Effective Mobility

${\mu}_{eff} = {\mu}_{o} \frac{E_{eff}}{E_{o}}^{\frac{-1}{3}}$