# Digital CMOS Design : CMOS Inverter,NAND, NOR Gate.

As the fate might have this, I am here again, a day before my viva, doing VLSI. Welcome to VLSI by an amateur who’s just trying to pass college exams. Warning: I know nothing, everything in this blog may or may not be write–or even make any sense.

## Taming the beast-Microwind

Microwind is a tool for designing and simulating circuits at a layout level.

• One dot grid in Microwind is 0.3 $\mu m$

## CMOS

• Complementary Metal Oxide Semiconductor
• Low Power Deception
• Consists of pMOS (Active Low) and nMOS (Active High). MOS is basically an ON and OFF switch
• Current can be adjusted by adjusting the width of the gate (Directly Proportional)

## CMOS – Complementary metal-oxide semiconductor

• CMOS has much lower power dissipation compared to its other BIPOLAR counterparts. * Insert inappropriate mental health jokes *
• Complementary MOS circuit has almost no static power dissipation.
• Complementary Metal Oxide Semiconductor transistor consists of P-channel MOS (PMOS) and N-channel MOS (NMOS). Please refer the link to know more about the fabrication process of CMOS transistor.
• Gate – Current is controls whether the device will be on or off.
• Drain and Source are identical, generally, the labelling convention says that terminal with higher potential is labelled as drain.
• Current from Drain to source is proportional to width of gate divided by length
• $I_{DS} = W/L$

## Thumb Rule to using pMOS and nMOS

• Use nMOS in circuits output node to ground(Logic 0) or pull down circuits
• Use pMOS in circuits output node to VDD(Logic 1) or pull up circuits

## Some Formulas $I_{lkg} = i_{s} (e^{\frac{qv}{kT}-1})$

• is = reverse saturation current
• V = diode voltage
• k = Boltzmann’s constant (1.38 × 10–23 J/K)
• q = electronic charge (1.602 × 10–19 C)
• T = temperature

PS = Summation { (leakage current) x (supply voltage)}

## CMOS Logic

• You will need to create two networks, one pull up that draws he circuit to VDD and pull-down that draws it to GND
• Create these two separately
• Single Gate : pMOS when it’s active low and nMOS when it’s active high.
• Two gates :pMOS in series == A’ . B’ or (A+B)’
• pMOS in parallel == A’+B’ or (A.B)’
• nMOS in series == A.B or (A+B)
• nMOS in parallel == A+B or (A.B)
• Trick : Make the nMOS circuit, whenever nMOS is in series make pMOS in parallel and vice versa.
• Trick2:Use nMOS in circuits output node to ground(Logic 0) or pull down circuits
• Use pMOS in circuits output node to VDD(Logic 1) or pull up circuits

## CMOS Inverter

Inverter is simple idea. Whatever input you get, you give the opposite of it back.

Inverter Logic Table

Thus, we know that when input is 0, nMOS will be on and when input is 1 pMOS will be active.

NOR CMOS

NOR CMOS