There are a lot of delays in verilog, and trust me when I say I am done with them!
There is your normal delay
#10 y =1; //10 unit delay
But there you can have a delay with identifier
parameter latency = 10; #latency y =1;
You can also now have an expression
parameter latency = 10; parameter delta = 5; #(latency+delta) y =1;
Then there is minimum, typical and maximum delay
but they are further divided into rise time, fall time and turn off
#(4:5:6 7:8:9 10:11:12) y =1;
There is intra-assignment delays, oh boy
y = #10 x+z; //x+z will be evaluated at t=0 but assigned at t=10
Revolutionary idea, let’s just also have zero delay control. What?
#0 x=1; //this statement will be executed last