# Verilog: Gate Level Multiplexers

Welcome back, I am here, writing another blog as I struggle to understand the syllabus for my t2 exam. To anyone who’s reading this for the first time, let me give you some context.

Whenever I am conflicted about what I am studying I write a blog. This is also helpful whenever I have to come back to certain things I studied. In general, I just think that this is just a good nice letter that I am leaving for the future Meghana who’s gonna be happy to find her old blogs.

Let’s get to it.

## What is a Multiplexer?

Multiplexer is many to one switch. It is used to select one of the inputs and give it to the output. These inputs are selected by select line. Let’s say the inputs are (i0, i1, i2, i3) and select lines are (s1 and s2)

Trick for representation : Whenever you see a 0, negate it.

## Designing multiplexer according to representation!

``````module multiplexer
(
i0,
i1,
i2,
i3,
s1,
s2,
out
);

input i0, i1, i2, i3;
input s1, s2;
output out;

wire not_s1, not_s2;

not (not_s1, s1);
not (not_s2, s2);

wire y0, y1, y2, y3;

and (y0, not_s1, not_s2, i0);
and (y1, not_s1, s2, i1);
and (y2, s1, not_s2, i2);
and (y3, s1, s2, i3);

or (out, y0, y1, y2, y3);

endmodule``````

## Now let’s write testbench

``````module multi_tb;
reg I0, I1, I2, I3, S1, S2;
wire OUT;
multiplexer mux1(I0, I1, I2, I3, S1, S2, OUT);
initial
begin
I0= 1'b1; I1=1'b0 ; I2=1'b0 ; I3= 1'b0; S1=1'b1 ; S2=1'b1;
#10;
\$display("I0 %b \nI1 %b \nI2 %b \nI3 %b \nS1 %b \nS2 %b \nOUT %b",I0, I1, I2, I3, S1, S2, OUT);
end

endmodule ``````

Important thing

I struggled a lot with this code, one thing to remember is that you need to add #10 to display the results. This is because everything is running simultaneously and you print the value of regs when they are at t=0 i.e they haven’t been passed through the module!

## 2:1 mux using bufif

This is also similar to transmission gates

So this was the question

``````module mux(
in1,
in2,
s,
out
);
input in1, in2, s;
output out;

bufif0 #(1:3:5, 2:4:6, 3:5:7) b1 (out, in1, s);
bufif1 #(1:3:5, 2:4:6, 3:5:7) b2 (out, in2, s);

endmodule``````
``````module mux_tb;
reg in1, in2, s;
wire out;

mux m1(
in1,
in2,
s,
out
);

initial
begin
in1 =1'b1;
in2 =1'b0;
s = 1'b0;
#10;
\$display("in1 = %b",in1);
\$display("in2 = %b",in2);
\$display("s = %b",s);
\$display("out = %b",out);

s = 1'b1;
#10;
\$display("in1 = %b",in1);
\$display("in2 = %b",in2);
\$display("s = %b",s);
\$display("out = %b",out);
end
endmodule``````
```in1 = 1
in2 = 0
s = 0
out = 1
in1 = 1
in2 = 0
s = 1
out = 0```