Continuous Assignment

Rules First

  • Left hand of the assignment must always be a scalar or vector net.
    • It cannot be a scalar or vector register
  • Continuous assignments are always active
    • Eval ASA right hand operand changes and value is assigned.
  • Right hand can be register or nets or function calls, they can also be scalars or vectors
assign addr[15:0] = addr1_bits[15:0] ^ addr2_bits[15:0]

Remember delays that we did last time, if you want to have delay in the assignment the same thing can be done here. Thus, now there will be a time delay when the right hand changes and the value is assigned to the lefthand.

assign #(10) addr[15:0] = addr1_bits[15:0] ^ addr2_bits[15:0] #adds 10 second delay

There are three of these delays.

Regular Assignment delay

assign #(10) b = a ^ b; 

Implicit Continuous Assignment Delay

wire #(10) b= a^b;

Net Declaration Delay

wire #(10) b;
b = a^b;


They combine operators and operands. This is pretty similar to a normal expression in any language.

a ^ b

Let’s talk about some interesting one

  1. Case Equality/inequality : Equates using x and z
  2. Reduction : Reduces it down to one bit by doing interbit operation
  3. Concatenation : Literally concatenates the binary numbers
  4. Replication : Concatenates and then replicates the numebers

Multiplexer Using Conditional operators and continuous assignment.

Truth table first.


let me write this as if else condition sudo code

if S1 is True: 
    if S0 True:
         output == I2
         output == I1
    if S0 True:
         output == I4
         output = I3

Now let’s convert it to a single line nested condition

S1 ? (S0 ? I2:I1) : (S0 ? I4 : I3)

So the module looks something like

module multiplexer (i1, i2, i3, i4, out, s0, s1)

input i1, i2, i3, i4; 
input s1, s0;
output out; 

assign out s1 ? (s0 ? i2:i1) : (s0 ? i4 : i3)


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