# Verilog : Hierarchical Modeling Concepts

## Hierarchical Modeling Concepts

• Modules are Building blacks
• You can either have top down where you break a model to it’s smallest primitives and bottom up where you start building from primitives
• Modules : Now modules are basic building blocks of Verilog
``````module MyModule ([parameters]);
inputs ...
outputs ...
internal variables ...
...
Module Code ...
endmodule``````
• Instance
``````wire w, x, y, z;
AND A1(w, x, y);
AND A2(w, y, z);
AND A3(z, x, w);``````

Reference

Hierarchical Modeling Concepts: VLSI

Turns out, I have a course in VLSI and today happens to be the first time I am opening up my textbook. To add to this spicy spicy story, it’s also the day (night) before my exam. Before you start freaking out and giving up on me, let me tell you one thing. IT IS AS BAD AS IT SOUNDS

Here’s the game plan of the night, I document everything I am learning simultaneously and hoping that I don’t do so bad in the exam that I need to reconsider my graduating options.

These are my notes of second chapter from  Verilog HDL: A Guide to Digital Design and Synthesis, Second Edition. By Samir Palnitkar.

Modeling Concepts is basically how you’re going to go about solving your problem. How are you going to build your modules and instances.

## Top down and Bottom Up methodology.

Top down methodology will be something like you have the idea of the final model in your head and then you keep breaking it down into smaller and smaller modules till you’re down to primitive modules in Verilog.

Bottom up on the other hand, you start off with a very primitive module and start putting these tiny building blocks on top of each other to build the final model.

Here’s an example of how it will look for a 4 bit ripple counter

## Modules

Now modules are basic building blocks of Verilog. I think of modules like an object in C++ (This is a crude correlation but it helps me clear up my thoughts a bit)

Learning is always easier when you try to learn by correlating new things with the information you already have.

``````module MyModule ([parameters]);
inputs ...
outputs ...
internal variables ...
...
Module Code ...
endmodule``````

### Things To Note:

• Starts with `module` ends with `endmodule`
• `inputs` and `outputs` are both taken in as `[parameters]`
• No specific order for input and output in `[parameters]`
• MODULE NESTING IS ILLEGAL

`input` and `output` here are ports, `MyModule` is an identifier (terminology is important if you want to score in exam)

• It is both a behavioral and structural language
• You can write module at four levels of abstractions
• Behavioural (Algorithmic like C)
• Dataflow (How data flows between resistors)
• Gate Level (Logic gate circuits)
• Switch Level (1s and 0s)

Higher the level of abstraction, the more flexible and technology independent the design is.

Verilog HDL: A Guide to Digital Design and Synthesis, Second Edition. By Samir Palnitkar.

## Instances

Instance of a Module is instance. To make it more clear, think of this as an object to a class in Java or C++

You can have instances of modules in definition of another module, but you cannot have declaration of the new module.

``````module AND(a, b, c);
input a, b;
output c;
assign c = a & b;
endmodule

wire w, x, y, z;
AND A1(w, x, y);
AND A2(w, y, z);
AND A3(z, x, w);

Reference``````

## Simulation

Now that you have your code ready you need to test it. This is usually done using a test bench or Stimulus. You can either give this directly to design block, or create a dummy interface (top level block) that will give signal to both stimulus and design block.

Stimulus is basically just another module which generates input and gives to out design block.

Think of this as writing python unit tests.

## Conclusion

• You have two design methods top down and bottom up. Combination of this is used.
• Modules are basic building blocks (They are like classes)
• Instances are unique instances of modules (Objects)
• Each instance has independent copy of variables.
• You will have a design block and stimulus block.

One chapter down, five more to go! Coffee–My ol’ friend.

Link to my annotated PDF for this chapter